39 search results - page 7 / 8 » Performance Optimization By Wire and Buffer Sizing Under The... |
EMSOFT
2007
Springer
14 years 1 months ago
2007
Springer
Design space exploration of embedded systems typically focuses on classical design goals such as cost, timing, buffer sizes, and power consumption. Robustness criteria, i.e. sensi...
TCOM
2008
13 years 7 months ago
2008
Abstract--Incremental-redundancy hybrid automatic repeatrequest (IR-HARQ) schemes are proposed in several wireless standards for increased throughput-efficiency and greater reliabi...
JSA
2007
13 years 7 months ago
2007
Mapping of applications on a Multiprocessor System-on-Chip (MP-SoC) is a crucial step to optimize performance, energy and memory constraints at the same time. The problem is formu...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...
AINA
2008
IEEE
14 years 2 months ago
2008
IEEE
Wireless Sensor Networks (WSN) have specific constraints and stringent requirements in contrast to traditional wired and wireless computer networks. Among these specific requireme...