As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-...
We present the results of a performance evaluation of link layer error recovery over wireless links. Our analysis is based upon a case study of the circuit-switched data service i...
Hierarchical penalization is a generic framework for incorporating prior information in the fitting of statistical models, when the explicative variables are organized in a hiera...
Marie Szafranski, Yves Grandvalet, Pierre Morizet-...
Algebraic transformation and optimization techniques have been the method of choice in relational query execution, but applying them in OODBMS is difficult due to the complexity o...
Peter A. Boncz, Annita N. Wilschut, Martin L. Kers...
We describe and analyze the joint source/channel coding properties of a class of sparse graphical codes based on compounding a low-density generator matrix (LDGM) code with a low-...