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ISCA
2007
IEEE
143views Hardware» more  ISCA 2007»
14 years 3 months ago
Interconnect design considerations for large NUCA caches
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
Naveen Muralimanohar, Rajeev Balasubramonian
JMLR
2008
151views more  JMLR 2008»
13 years 8 months ago
Learning to Combine Motor Primitives Via Greedy Additive Regression
The computational complexities arising in motor control can be ameliorated through the use of a library of motor synergies. We present a new model, referred to as the Greedy Addit...
Manu Chhabra, Robert A. Jacobs
WWW
2009
ACM
14 years 9 months ago
Highly scalable web applications with zero-copy data transfer
The performance of server-side applications is becoming increasingly important as more applications exploit the Web application model. Extensive work has been done to improve the ...
Toyotaro Suzumura, Michiaki Tatsubori, Scott Trent...
ICML
2005
IEEE
14 years 9 months ago
Core Vector Regression for very large regression problems
In this paper, we extend the recently proposed Core Vector Machine algorithm to the regression setting by generalizing the underlying minimum enclosing ball problem. The resultant...
Ivor W. Tsang, James T. Kwok, Kimo T. Lai
CODES
2004
IEEE
14 years 14 days ago
Multi-objective mapping for mesh-based NoC architectures
In this paper we present an approach to multi-objective exploration of the mapping space of a mesh-based network-on-chip architecture. Based on evolutionary computing techniques, ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi