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» Performance Studies of a Parallel Prolog Architecture
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HPCA
2008
IEEE
14 years 8 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
IPPS
2010
IEEE
13 years 6 months ago
Optimizing and tuning the fast multipole method for state-of-the-art multicore architectures
This work presents the first extensive study of singlenode performance optimization, tuning, and analysis of the fast multipole method (FMM) on modern multicore systems. We consid...
Aparna Chandramowlishwaran, Samuel Williams, Leoni...
ICPP
1998
IEEE
14 years 22 days ago
Performance Implications of Architectural and Software Techniques on I/O-Intensive Applications
Many large scale applications, have significant I/O requirements as well as computational and memory requirements. Unfortunately, limited number of I/O nodes provided by the conte...
Meenakshi A. Kandaswamy, Mahmut T. Kandemir, Alok ...
APPT
2009
Springer
14 years 3 months ago
Performance Improvement of Multimedia Kernels by Alleviating Overhead Instructions on SIMD Devices
SIMD extension is one of the most common and effective technique to exploit data-level parallelism in today’s processor designs. However, the performance of SIMD architectures i...
Asadollah Shahbahrami, Ben H. H. Juurlink
HPCN
1995
Springer
14 years 20 hour ago
A hierarchical approach to workload characterization for parallel systems
Performance evaluation studies are to be an integral part of the design and tuning of parallel applications. We propose a hierarchical approach to the systematic characterization o...
Maria Calzarossa, Alessandro P. Merlo, Daniele Tes...