372 search results - page 20 / 75 » Performance Studies of a Parallel Prolog Architecture |
HIPC
2009
Springer
13 years 6 months ago
2009
Springer
The significant growth in computational power of modern Graphics Processing Units(GPUs) coupled with the advent of general purpose programming environments like NVIDA's CUDA,...
EUROPAR
2009
Springer
14 years 3 months ago
2009
Springer
Moore’s Law suggests that the number of processing cores on a single chip increases exponentially. The future performance increases will be mainly extracted from thread-level par...
IEEEPACT
2006
IEEE
14 years 2 months ago
2006
IEEE
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
ICPP
1997
IEEE
14 years 21 days ago
1997
IEEE
Communication characterization of parallel applications is essential to understand the interplay between architectures and applications in determining the maximum achievable perfo...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
We present a study of multithreaded implementations of Thorup’s algorithm for solving the Single Source Shortest Path (SSSP) problem for undirected graphs. Our implementations l...