372 search results - page 48 / 75 » Performance Studies of a Parallel Prolog Architecture |
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
HPCA
2000
IEEE
14 years 28 days ago
2000
IEEE
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction, and executes speculatively its data-dependent instructions based on ...
CCGRID
2001
IEEE
14 years 5 days ago
2001
IEEE
Virtual Interface Architecture(VIA) is a light-weight protocol for protected user-level zero-copy communication. In spite of high performance of VIA, the previous MPI implementati...
CF
2009
ACM
14 years 3 months ago
2009
ACM
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
EUROPAR
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. Simulation platforms for network processing still have difficulties in finding a good compromise between speed and accuracy. This makes it difficult to identify the caus...