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» Performance analysis of a user-level memory server
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PLDI
2012
ACM
11 years 9 months ago
Scalable and precise dynamic datarace detection for structured parallelism
Existing dynamic race detectors suffer from at least one of the following three limitations: (i) space overhead per memory location grows linearly with the number of parallel thre...
Raghavan Raman, Jisheng Zhao, Vivek Sarkar, Martin...
POPL
2006
ACM
14 years 7 months ago
Autolocker: synchronization inference for atomic sections
The movement to multi-core processors increases the need for simpler, more robust parallel programming models. Atomic sections have been widely recognized for their ease of use. T...
Bill McCloskey, Feng Zhou, David Gay, Eric A. Brew...
ISPD
2003
ACM
133views Hardware» more  ISPD 2003»
14 years 19 days ago
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-si...
Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Pin...
IMC
2006
ACM
14 years 1 months ago
Approximate fingerprinting to accelerate pattern matching
Pattern matching and analysis over network data streams is increasingly becoming an essential primitive of network monitoring systems. It is a fundamental part of most intrusion d...
Ramaswamy Ramaswamy, Lukas Kencl, Gianluca Iannacc...
CF
2006
ACM
13 years 9 months ago
Intermediately executed code is the key to find refactorings that improve temporal data locality
The growing speed gap between memory and processor makes an efficient use of the cache ever more important to reach high performance. One of the most important ways to improve cac...
Kristof Beyls, Erik H. D'Hollander