108 search results - page 14 / 22 » Performance and Power Impact of Issue-width in Chip-Multipro... |
ICPP
2009
IEEE
13 years 5 months ago
2009
IEEE
This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this c...
HIPEAC
2009
Springer
13 years 11 months ago
2009
Springer
Shrinking process technologies and growing chip sizes have profound effects on process variation. This leads to Chip Multiprocessors (CMPs) where not all cores operate at maximum f...
SC
2009
ACM
14 years 2 months ago
2009
ACM
Continuous evolution in process technology brings energyefficiency and reliability challenges, which are harder for memory system designs since chip multiprocessors demand high ba...
ASPLOS
2008
ACM
13 years 9 months ago
2008
ACM
Extracting high-performance from the emerging Chip Multiprocessors (CMPs) requires that the application be divided into multiple threads. Each thread executes on a separate core t...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
Multi-core architectures introduce a new granularity at which process variations may occur, yielding asymmetry among cores that were designed—and that software expects—to be s...