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OTM
2007
Springer
14 years 2 months ago
Parallelizing Tableaux-Based Description Logic Reasoning
Practical scalability of Description Logic (DL) reasoning is an important premise for the adoption of OWL in a real-world setting. Many highly efficient optimizations for the DL ta...
Thorsten Liebig, Felix Müller
ASPLOS
2011
ACM
13 years 11 days ago
Inter-core prefetching for multicore processors using migrating helper threads
Multicore processors have become ubiquitous in today’s systems, but exploiting the parallelism they offer remains difficult, especially for legacy application and applications ...
Md Kamruzzaman, Steven Swanson, Dean M. Tullsen
DAC
1997
ACM
14 years 29 days ago
COSYN: Hardware-Software Co-Synthesis of Embedded Systems
: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power and cost goals. In t...
Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. J...
IOPADS
1997
152views more  IOPADS 1997»
13 years 10 months ago
Competitive Parallel Disk Prefetching and Buffer Management
We provide a competitive analysis framework for online prefetching and buffer management algorithms in parallel I/O systems, using a read-once model of block references. This has ...
Rakesh D. Barve, Mahesh Kallahalla, Peter J. Varma...
CGO
2006
IEEE
14 years 2 months ago
Thread-Shared Software Code Caches
Software code caches are increasingly being used to amortize the runtime overhead of dynamic optimizers, simulators, emulators, dynamic translators, dynamic compilers, and other t...
Derek Bruening, Vladimir Kiriansky, Timothy Garnet...