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HPCA
2000
IEEE
14 years 1 months ago
Design of a Parallel Vector Access Unit for SDRAM Memory Systems
We are attacking the memory bottleneck by building a “smart” memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting appl...
Binu K. Mathew, Sally A. McKee, John B. Carter, Al...
CC
2008
Springer
144views System Software» more  CC 2008»
13 years 11 months ago
Control Flow Emulation on Tiled SIMD Architectures
Heterogeneous multi-core and streaming architectures such as the GPU, Cell, ClearSpeed, and Imagine processors have better power/ performance ratios and memory bandwidth than tradi...
Ghulam Lashari, Ondrej Lhoták, Michael McCo...
ICRA
2010
IEEE
142views Robotics» more  ICRA 2010»
13 years 7 months ago
Toward automated tissue retraction in robot-assisted surgery
—Robotic surgical assistants are enhancing physician performance, enabling physicians to perform more delicate and precise minimally invasive surgery. However, these devices are ...
Sachin Patil, Ron Alterovitz
MOBISYS
2010
ACM
13 years 11 months ago
MAUI: making smartphones last longer with code offload
This paper presents MAUI, a system that enables fine-grained energy-aware offload of mobile code to the infrastructure. Previous approaches to these problems either relied heavily...
Eduardo Cuervo, Aruna Balasubramanian, Dae-ki Cho,...
SENSYS
2006
ACM
14 years 3 months ago
Capsule: an energy-optimized object storage system for memory-constrained sensor devices
Recent gains in energy-efficiency of new-generation NAND flash storage have strengthened the case for in-network storage by data-centric sensor network applications. This paper ...
Gaurav Mathur, Peter Desnoyers, Deepak Ganesan, Pr...