157 search results - page 17 / 32 » Performance area efficiency in chip multiprocessors with mic... |
ISQED
2007
IEEE
14 years 2 months ago
2007
IEEE
The virtual channel flow control (VCFC) provides an efficient implementation for on-chip networks. However, allocating the virtual channels (VCs) uniformly results in a waste of a...
ESTIMEDIA
2006
Springer
14 years 8 days ago
2006
Springer
Efficient and deadlock-free routing is critical to the performance of networks-on-chip. In this paper we present an approach that can be coupled to any adaptive routing algorithm ...
ISCA
2009
IEEE
14 years 3 months ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
ISCA
1996
IEEE
14 years 23 days ago
1996
IEEE
Parallel workstations, each comprising 10-100 processors, promise cost-effective general-purpose multiprocessing. This paper explores the coupling of such small- to medium-scale s...
ISCAS
2008
IEEE
14 years 3 months ago
2008
IEEE
— In this paper we present implementation and experimental results for a digital vision chip that operates in mixed asynchronous/synchronous mode. Mixed configuration benefits fr...