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VLSID
2007
IEEE
206views VLSI» more  VLSID 2007»
14 years 9 months ago
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
IEEEPACT
2005
IEEE
14 years 2 months ago
Maximizing CMP Throughput with Mediocre Cores
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use...
John D. Davis, James Laudon, Kunle Olukotun
WSC
1997
13 years 10 months ago
Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
Peter S. Magnusson
FPL
2006
Springer
242views Hardware» more  FPL 2006»
14 years 8 days ago
TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
Manuel Saldaña, Paul Chow
ICASSP
2008
IEEE
14 years 3 months ago
Efficient assignment algorithm for mapping multidimensional signals into the physical memory
The storage requirements in data-intensive multidimensional signal processing systems have a significant impact on the system performance as well as on essential design parameter...
Ilie I. Luican, Hongwei Zhu, Florin Balasa