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NOCS
2007
IEEE
14 years 2 months ago
Implementation and Evaluation of a Dynamically Routed Processor Operand Network
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...
Paul Gratz, Karthikeyan Sankaralingam, Heather Han...
LCN
2007
IEEE
14 years 2 months ago
Node Connectivity in Vehicular Ad Hoc Networks with Structured Mobility
1 Vehicular Ad hoc NETworks (VANETs) is a subclass of Mobile Ad hoc NETworks (MANETs). However, automotive ad hoc networks will behave in fundamentally different ways than the pred...
Ivan Wang Hei Ho, Kin K. Leung, John W. Polak, Rah...
SIGCOMM
2006
ACM
14 years 2 months ago
Analyzing the MAC-level behavior of wireless networks in the wild
We present Wit, a non-intrusive tool that builds on passive monitoring to analyze the detailed MAC-level behavior of operational wireless networks. Wit uses three processing steps...
Ratul Mahajan, Maya Rodrig, David Wetherall, John ...
HPCA
2009
IEEE
14 years 9 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
PE
2008
Springer
143views Optimization» more  PE 2008»
13 years 8 months ago
Improving the performance of large interconnection networks using congestion-control mechanisms
As the size of parallel computers increases, as well as the number of sources per router node, congestion inside the interconnection network rises significantly. In such systems, ...
José Miguel-Alonso, Cruz Izu, José-&...