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» Performance improvement with circuit-level speculation
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IEEEPACT
2009
IEEE
14 years 3 months ago
Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading
Industry is moving towards multi-core designs as we have hit the memory and power walls. Multi-core designs are very effective to exploit thread-level parallelism (TLP) but do not...
Carlos Madriles, Pedro López, Josep M. Codi...
LCPC
2005
Springer
14 years 1 months ago
Loop Selection for Thread-Level Speculation
Thread-level speculation (TLS) allows potentially dependent threads to speculatively execute in parallel, thus making it easier for the compiler to extract parallel threads. Howeve...
Shengyue Wang, Xiaoru Dai, Kiran Yellajyosula, Ant...
IPPS
2010
IEEE
13 years 6 months ago
On the parallelisation of MCMC by speculative chain execution
Abstract--The increasing availability of multi-core and multiprocessor architectures provides new opportunities for improving the performance of many computer simulations. Markov C...
Jonathan M. R. Byrd, Stephen A. Jarvis, Abhir H. B...
CGO
2004
IEEE
14 years 5 days ago
Compiler Optimization of Memory-Resident Value Communication Between Speculative Threads
Efficient inter-thread value communication is essential for improving performance in Thread-Level Speculation (TLS). Although several mechanisms for improving value communication ...
Antonia Zhai, Christopher B. Colohan, J. Gregory S...
OSDI
2008
ACM
14 years 8 months ago
Improving MapReduce Performance in Heterogeneous Environments
MapReduce is emerging as an important programming model for large-scale data-parallel applications such as web indexing, data mining, and scientific simulation. Hadoop is an open-...
Matei Zaharia, Andy Konwinski, Anthony D. Joseph, ...