176 search results - page 20 / 36 » Performance improvement with circuit-level speculation |
COMPUTE
2010
ACM
13 years 11 months ago
2010
ACM
In the literature, speculation-based protocols have been proposed to improve the performance of read-only transactions (ROTs) over the existing two-phase locking (2PL) and snapsho...
EUROPAR
2005
Springer
14 years 28 days ago
2005
Springer
Instruction delivery is a critical component for wide-issue processors since its bandwidth and accuracy place an upper limit on performance. The processor front-end accuracy and ba...
CF
2006
ACM
14 years 1 months ago
2006
ACM
There is a continuous research effort devoted to overcome the memory wall problem. Prefetching is one of the most frequently used techniques. A prefetch mechanism anticipates the ...
ISCA
1996
IEEE
13 years 11 months ago
1996
IEEE
Many studies have investigated performance improvement through exploiting instruction-level parallelism (ILP) with a particular architecture. Unfortunately, these studies indicate...
HPCA
2000
IEEE
13 years 11 months ago
2000
IEEE
Efficiency of synchronization mechanisms can limit the parallel performance of many shared-memory applications. In addition, the ever increasing performance gap between processor...