176 search results - page 7 / 36 » Performance improvement with circuit-level speculation |
CF
2007
ACM
14 years 12 days ago
2007
ACM
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded...
ASPLOS
2000
ACM
14 years 24 days ago
2000
ACM
Processors execute the full dynamic instruction stream to arrive at the final output of a program, yet there exist shorter instruction streams that produce the same overall effec...
HPCA
1999
IEEE
14 years 22 days ago
1999
IEEE
We propose Instruction-based Prediction as a means to optimize directory-based cache coherent NUMA shared-memory. Instruction-based prediction is based on observing the behavior o...
MICRO
1997
IEEE
14 years 19 days ago
1997
IEEE
As processors continue to exploit more instruction level parallelism, a greater demand is placed on reducing the e ects of memory access latency. In this paper, we introduce a nov...