143 search results - page 11 / 29 » Performance metric alerting: a new design approach for compl... |
JPDC
2007
13 years 7 months ago
2007
In this paper, we address the problem of multiple sequence alignment (MSA) for handling very large number of proteins sequences on mesh-based multiprocessor architectures. As the ...
ITC
2002
IEEE
14 years 26 days ago
2002
IEEE
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
AHS
2007
IEEE
13 years 12 months ago
2007
IEEE
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
Performance and workload modeling has numerous uses at every stage of the high-end computing lifecycle: design, integration, procurement, installation and tuning. Despite the trem...
AINA
2005
IEEE
14 years 1 months ago
2005
IEEE
Input Buffered Switches with Virtual Output Queues(VOQ) design to avoid Head-Of-Line problems, is a primary design of switches that can be scalable to very high speeds. However, t...