We present the performance of three different multivalued current mode 1-bit adders. These circuits have been simulated with the electrical parameters of a
— A new operation mode using a partially depleted hybrid lateral BJT-CMOS inverter on SOI, named as a new unified-BiCMOS (U-BiCMOS) inverter, is proposed. The scheme utilizes the...
In this paper a new low power and high performance adder cell using a new design style called "Bridge" is proposed. The bridge design style enjoys a high degree of regula...
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...