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» Performance of Hardware Compressed Main Memory
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ACSD
2003
IEEE
103views Hardware» more  ACSD 2003»
14 years 1 months ago
Design Validation of ZCSP with SPIN
— We consider the problem of specifying a model of the Zero Copy Secured Protocol for the purpose of LTL verification with the SPIN Model Checker. ZCSP is based on Direct Memory...
Vincent Beaudenon, Emmanuelle Encrenaz, Jean Lou D...
ICS
1998
Tsinghua U.
14 years 10 days ago
OPTNET: A Cost-effective Optical Network for Multiprocessors
In this paper we propose the OPTNET, a novel optical network and associated coherence protocol for scalable multiprocessors. The network divides its channels into broadcast and po...
Enrique V. Carrera, Ricardo Bianchini
MICRO
1997
IEEE
128views Hardware» more  MICRO 1997»
14 years 10 days ago
Run-Time Spatial Locality Detection and Optimization
As the disparity between processor and main memory performance grows, the number of execution cycles spent waiting for memory accesses to complete also increases. As a result, lat...
Teresa L. Johnson, Matthew C. Merten, Wen-mei W. H...
ISCA
2012
IEEE
261views Hardware» more  ISCA 2012»
11 years 10 months ago
RAIDR: Retention-aware intelligent DRAM refresh
Dynamic random-access memory (DRAM) is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent loss of data. These refresh operation...
Jamie Liu, Ben Jaiyen, Richard Veras, Onur Mutlu
ASPLOS
2010
ACM
13 years 11 months ago
Orthrus: efficient software integrity protection on multi-cores
This paper proposes an efficient hardware/software system that significantly enhances software security through diversified replication on multi-cores. Recent studies show that a ...
Ruirui Huang, Daniel Y. Deng, G. Edward Suh