69 search results - page 10 / 14 » Performance of Switch Blocking on Multithreaded Architecture... |
CONEXT
2009
ACM
13 years 11 months ago
2009
ACM
Shipping-container-based data centers have been introduced as building blocks for constructing mega-data centers. However, it is a challenge on how to interconnect those container...
HPCA
2012
IEEE
12 years 5 months ago
2012
IEEE
Multiprocessor architectures that continuously execute atomic blocks (or chunks) of instructions can improve performance and software productivity. However, all of the prior propo...
MICRO
2005
IEEE
14 years 3 months ago
2005
IEEE
Data prefetching via helper threading has been extensively investigated on Simultaneous MultiThreading (SMT) or Virtual Multi-Threading (VMT) architectures. Although reportedly la...
FPGA
2005
ACM
14 years 3 months ago
2005
ACM
Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
SDL
2003
13 years 11 months ago
2003
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...