69 search results - page 2 / 14 » Performance of Switch Blocking on Multithreaded Architecture... |
IPPS
2009
IEEE
14 years 4 months ago
2009
IEEE
In this paper we explore the impact of the block shape on blocked and vectorized versions of the Sparse Matrix-Vector Multiplication (SpMV) kernel and build upon previous work by ...
BROADNETS
2004
IEEE
14 years 1 months ago
2004
IEEE
The paper1 presents and compares various unicast nonblocking architectures to be used into space-domain photonic switching networks. All the analyzed architectures have been evalu...
IPPS
2010
IEEE
13 years 7 months ago
2010
IEEE
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
ISCA
1994
IEEE
14 years 1 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
ISCA
2012
IEEE
12 years 6 days ago
2012
IEEE
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...