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FPL
2008
Springer
110views Hardware» more  FPL 2008»
13 years 9 months ago
Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip
While there have been many reported implementations of Networks-on-Chip (NoCs) on FPGAs, they have not seen the same acceptance as NoCs on ASICs. One reason is that communication ...
Matthew Shelburne, Cameron Patterson, Peter Athana...
IPPS
2008
IEEE
14 years 2 months ago
High performance MPEG-2 software decoder on the cell broadband engine
The Sony-Toshiba-IBM Cell Broadband Engine is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD coprocessing units (SPEs) ...
David A. Bader, Sulabh Patel
HPDC
2002
IEEE
14 years 17 days ago
Dynamic Right-Sizing in FTP (drsFTP): Enhancing Grid Performance in User-Space
With the advent of computational grids, networking performance over the wide-area network (WAN) has become a critical component in the grid infrastructure. Unfortunately, many hig...
Mark K. Gardner, Wu-chun Feng, Mike Fisk
GRID
2006
Springer
13 years 7 months ago
Multi-Replication with Intelligent Staging in Data-Intensive Grid Applications
Existing data grid scheduling systems handle huge data I/O via replica location services coupled with simple staging, decoupled from scheduling of computing tasks. However, when th...
Yuya Machida, Shin'ichiro Takizawa, Hidemoto Nakad...
CLUSTER
2009
IEEE
14 years 2 months ago
Integrating software distributed shared memory and message passing programming
Abstract—Software Distributed Shared Memory (SDSM) systems provide programmers with a shared memory programming environment across distributed memory architectures. In contrast t...
H'sien J. Wong, Alistair P. Rendell