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SAC
2008
ACM
15 years 2 months ago
Exploiting program cyclic behavior to reduce memory latency in embedded processors
In this work we modify the conventional row buffer allocation mechanism used in DDR2 SDRAM banks to improve average memory latency and overall processor performance. Our method as...
Ehsan Atoofian, Amirali Baniasadi
120
Voted
APPT
2007
Springer
15 years 8 months ago
Replication-Based Partial Dynamic Scheduling on Heterogeneous Network Processors
It is a great challenge to map network processing tasks to processing resources of advanced network processors, which are heterogeneous and multi-threading multiprocessor System-on...
Zhiyong Yu, Zhiyi Yang, Fan Zhang, Zhiwen Yu, Tuan...
141
Voted
IPPS
1999
IEEE
15 years 6 months ago
Reducing Parallel Overheads Through Dynamic Serialization
If parallelism can be successfully exploited in a program, significant reductions in execution time can be achieved. However, if sections of the code are dominated by parallel ove...
Michael Voss, Rudolf Eigenmann
VLDB
2005
ACM
117views Database» more  VLDB 2005»
15 years 8 months ago
Parallel Querying with Non-Dedicated Computers
We present DITN, a new method of parallel querying based on dynamic outsourcing of join processing tasks to non-dedicated, heterogeneous computers. In DITN, partitioning is not th...
Vijayshankar Raman, Wei Han, Inderpal Narang
128
Voted
HPCA
2005
IEEE
15 years 8 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...