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LCTRTS
2007
Springer
14 years 1 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
VLDB
2002
ACM
108views Database» more  VLDB 2002»
13 years 7 months ago
Generic Database Cost Models for Hierarchical Memory Systems
Accurate prediction of operator execution time is a prerequisite for database query optimization. Although extensively studied for conventional disk-based DBMSs, cost modeling in ...
Stefan Manegold, Peter A. Boncz, Martin L. Kersten
TON
2008
87views more  TON 2008»
13 years 7 months ago
Large-scale network parameter configuration using an on-line simulation framework
As the Internet infrastructure grows to support a variety of services, its legacy protocols are being overloaded with new functions such as traffic engineering. Today, operators en...
Tao Ye, Hema Tahilramani Kaur, Shivkumar Kalyanara...
TCOM
2010
115views more  TCOM 2010»
13 years 6 months ago
QoS Analysis of a Scheduling Policy for Heterogeneous Users Employing AMC Jointly with ARQ
—This paper analyzes the quality of service (QoS) of scheduling algorithms for heterogeneous users in multiuser (MU) wireless systems that take advantage from a crosslayer design...
Mario Poggioni, Luca Rugini, Paolo Banelli
MSS
2003
IEEE
151views Hardware» more  MSS 2003»
14 years 25 days ago
Accurate Modeling of Cache Replacement Policies in a Data Grid
Caching techniques have been used to improve the performance gap of storage hierarchies in computing systems. In data intensive applications that access large data files over wid...
Ekow J. Otoo, Arie Shoshani