955 search results - page 19 / 191 » Performance optimization of multiple memory architectures fo... |
152
Voted
ICPP
2008
IEEE
15 years 9 months ago
2008
IEEE
Abstract—The Sparse Matrix-Vector Multiplication kernel exhibits limited potential for taking advantage of modern shared memory architectures due to its large memory bandwidth re...
125
Voted
ARCS
2009
Springer
15 years 9 months ago
2009
Springer
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
124
Voted
HPCA
1995
IEEE
15 years 6 months ago
1995
IEEE
Information on the behavior of programs is essential for deciding the number and nature of functional units in high performance architectures. In this paper, we present studies on...
143
Voted
APCSAC
2004
IEEE
15 years 6 months ago
2004
IEEE
Dynamic optimization presents opportunities for finding run-time bottlenecks and deploying optimizations in statically compiled programs. In this paper, we discuss our current impl...
140
Voted
ISCA
1996
IEEE
15 years 6 months ago
1996
IEEE
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...