Sciweavers

955 search results - page 23 / 191
» Performance optimization of multiple memory architectures fo...
Sort
View
CHI
2006
ACM
14 years 9 months ago
Generating automated predictions of behavior strategically adapted to specific performance objectives
It has been well established in Cognitive Psychology that humans are able to strategically adapt performance, even highly skilled performance, to meet explicit task goals such as ...
Katherine Eng, Richard L. Lewis, Irene Tollinger, ...
WMPI
2004
ACM
14 years 2 months ago
Compiler-optimized usage of partitioned memories
In order to meet the requirements concerning both performance and energy consumption in embedded systems, new memory architectures are being introduced. Beside the well-known use o...
Lars Wehmeyer, Urs Helmig, Peter Marwedel
TJS
2008
95views more  TJS 2008»
13 years 9 months ago
Combating I-O bottleneck using prefetching: model, algorithms, and ramifications
Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter [?]. More than a decade of architectural a...
Akshat Verma, Sandeep Sen
VLSID
2007
IEEE
133views VLSI» more  VLSID 2007»
14 years 9 months ago
On the Impact of Address Space Assignment on Performance in Systems-on-Chip
Today, VLSI systems for computationally demanding applications are being built as Systems-on-Chip (SoCs) with a distributed memory sub-system which is shared by a large number of ...
G. Hazari, Madhav P. Desai, H. Kasture
TC
1998
13 years 8 months ago
Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors
—We evaluate three extensions to directory-based cache coherence protocols in shared-memory multiprocessors. These extensions are aimed at reducing the penalties associated with ...
Fredrik Dahlgren, Michel Dubois, Per Stenströ...