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ISCAS
2011
IEEE
12 years 11 months ago
2011
IEEE
— The last two decades have seen many efficient algorithms and architectures for the design of low-complexity bit-parallel Multiple Constant Multiplications (MCM) operation, tha...
ISCAPDCS
2001
13 years 9 months ago
2001
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...
CASES
2007
ACM
13 years 11 months ago
2007
ACM
In this paper we describe the design and implementation of a flexible, and extensible, just-in-time ARM simulator designed to run co-operatively with a multi-core DSP simulator on...
CASES
2007
ACM
13 years 11 months ago
2007
ACM
Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local...
HIPEAC
2007
Springer
14 years 1 months ago
2007
Springer
The XScale processor family provides user-controllable independent configuration of CPU, bus, and memory frequencies. This feature introduces another handle for the code optimizat...