955 search results - page 50 / 191 » Performance optimization of multiple memory architectures fo... |
GLVLSI
2007
IEEE
14 years 29 days ago
2007
IEEE
This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation o...
EVOW
2008
Springer
13 years 10 months ago
2008
Springer
The design of computer architectures requires the setting of multiple parameters on which the final performance depends. The number of possible combinations make an extremely huge ...
GECCO
2010
Springer
13 years 9 months ago
2010
Springer
In this paper we present a concurrent implementation of genetic algorithms designed for shared memory architectures intended to take advantage of multi-core processor platforms. O...
TEC
2008
13 years 9 months ago
2008
In recent years, interest in studying evolutionary algorithms (EAs) for dynamic optimization problems (DOPs) has grown due to its importance in real-world applications. Several app...
ICASSP
2011
IEEE
13 years 24 days ago
2011
IEEE
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...