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ISLPED
2010
ACM
183views Hardware» more  ISLPED 2010»
13 years 7 months ago
A pareto-algebraic framework for signal power optimization in global routing
This paper proposes a framework for (signal) interconnect power optimization at the global routing stage. In a typical design flow, the primary objective of global routing is mini...
Hamid Shojaei, Tai-Hsuan Wu, Azadeh Davoodi, Twan ...
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
13 years 12 months ago
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
Cheng-Kok Koh, Patrick H. Madden
VLSID
1999
IEEE
104views VLSI» more  VLSID 1999»
13 years 11 months ago
Interconnect Optimization Strategies for High-Performance VLSI Designs
Interconnect tuning and repeater insertion are necessary to optimize interconnectdelay, signalperformanceandintegrity, andinterconnectmanufacturability and reliability. Repeater i...
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
IJIPT
2008
114views more  IJIPT 2008»
13 years 7 months ago
Enabling global multimedia distributed services based on hierarchical DHT overlay networks
The provision of innovating multimedia services is a high priority for service providers. Due to the the high traffic volume characteristics of multimedia content, decentralised s...
Isaías Martinez-Yelmo, Alex Bikfalvi, Carme...
DATE
1998
IEEE
91views Hardware» more  DATE 1998»
13 years 11 months ago
Interconnect Tuning Strategies for High-Performance Ics
Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of lin...
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahu...