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SAC
2008
ACM
13 years 7 months ago
Exploiting program cyclic behavior to reduce memory latency in embedded processors
In this work we modify the conventional row buffer allocation mechanism used in DDR2 SDRAM banks to improve average memory latency and overall processor performance. Our method as...
Ehsan Atoofian, Amirali Baniasadi
CGO
2010
IEEE
14 years 2 months ago
Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bi
For memory constrained embedded systems code size is at least as important as performance. One way of increasing code density is to exploit compact instruction formats, e.g. ARM T...
Tobias J. K. Edler von Koch, Igor Böhm, Bj&ou...
ICPP
1993
IEEE
13 years 11 months ago
A Concurrent Dynamic Task Graph
Task graphs are used for scheduling tasks on parallel processors when the tasks have dependencies. If the execution of the program is known ahead of time, then the tasks can be st...
Theodore Johnson
ISCAS
2007
IEEE
101views Hardware» more  ISCAS 2007»
14 years 1 months ago
Flexible and Cost Effective Transport Stream Processor for DTV
— A flexible transport stream processor for DTV which is also designed under cost-effective consideration is proposed in this paper. A RISC micro-controller is allocated as the ...
Chia-Liang Tsai, Shao-Yi Chien
ISVLSI
2003
IEEE
118views VLSI» more  ISVLSI 2003»
14 years 23 days ago
Reconfigurable Fast Memory Management System Design for Application Specific Processors
This paper presents the design and implementation of the new Active Memory Manager Unit (AMMU) designed to be embedded into System-on-Chip CPUs. The unit is implemented using VHDL...
S. Kagan Agun, J. Morris Chang