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MICRO
1992
IEEE
99views Hardware» more  MICRO 1992»
14 years 1 months ago
An investigation of the performance of various dynamic scheduling techniques
An important design decision in the implementation of a superscalar processor is the amount of hardware to allocate to the instruction scheduling mechanism. Dynamic scheduling pro...
Michael Butler, Yale N. Patt
DAC
1995
ACM
14 years 1 months ago
Code Optimization Techniques for Embedded DSP Microprocessors
—We address the problem of code optimization for embedded DSP microprocessors. Such processors (e.g., those in the TMS320 series) have highly irregular datapaths, and conventiona...
Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Stev...
ISCA
1991
IEEE
110views Hardware» more  ISCA 1991»
14 years 1 months ago
Dynamic Base Register Caching: A Technique for Reducing Address Bus Width
When address reference streams exhibit high degrees of spatial and temporal locality, many of the higher order address lines carry redundant information. By caching the higher ord...
Matthew K. Farrens, Arvin Park
ANCS
2008
ACM
13 years 11 months ago
On runtime management in multi-core packet processing systems
Computer networks require increasingly complex packet processing in the data path to adapt to new functionality requirements. To meet performance demands, packet processing system...
Qiang Wu, Tilman Wolf
GPC
2008
Springer
13 years 10 months ago
Using Moldability to Improve Scheduling Performance of Parallel Jobs on Computational Grid
In a computational grid environment, a common practice is try to allocate an entire parallel job onto a single participating site. Sometimes a parallel job, upon its submission, ca...
Kuo-Chan Huang, Po-Chi Shih, Yeh-Ching Chung