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IEEEPACT
2007
IEEE
14 years 3 months ago
A Flexible Heterogeneous Multi-Core Architecture
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
Miquel Pericàs, Adrián Cristal, Fran...
ISCAPDCS
2003
13 years 11 months ago
Utilization of Separate Caches to Eliminate Cache Pollution Caused by Memory Management Functions
Data intensive service functions such as memory allocation/de-allocation, data prefetching, and data relocation can pollute processor cache in conventional systems since the same ...
Mehran Rezaei, Krishna M. Kavi
GRID
2006
Springer
13 years 9 months ago
Metascheduling Multiple Resource Types using the MMKP
Grid computing involves the transparent sharing of computational resources of many types by users across large geographic distances. The altruistic nature of many current grid reso...
Daniel C. Vanderster, Nikitas J. Dimopoulos, Randa...
MICRO
2010
IEEE
167views Hardware» more  MICRO 2010»
13 years 7 months ago
Erasing Core Boundaries for Robust and Configurable Performance
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address thes...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott ...
CASES
2009
ACM
13 years 7 months ago
Spatial complexity of reversibly computable DAG
In this paper we address the issue of making a program reversible in terms of spatial complexity. Spatial complexity is the amount of memory/register locations required for perfor...
Mouad Bahi, Christine Eisenbeis