1493 search results - page 219 / 299 » Petascale computing with accelerators |
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
PARELEC
2006
IEEE
14 years 1 months ago
2006
IEEE
processor arrays can be used as accelerators for a plenty of data flow-dominant applications. The explosive growth in research and development of massively parallel processor arr...
ACCV
2006
Springer
14 years 1 months ago
2006
Springer
We developed a system including two modules: the texture analysis module and the texture synthesis module. The analysis module is capable of analyzing an input image and performing...
ANCS
2006
ACM
14 years 1 months ago
2006
ACM
The increase of the web traffic has created the need for web switches that are able to balance the traffic to the server farms based on their contents (e.g. layer 7 switching). In...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
— Balanced truncation (BT) model order reduction (MOR) is known for its superior accuracy and computable error bounds. Balanced stochastic truncation (BST) is a particular BT pro...