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ANCS
2010
ACM
13 years 5 months ago
sNICh: efficient last hop networking in the data center
: sNICh: Efficient Last Hop Networking in the Data Center Kaushik Kumar Ram, Jayaram Mudigonda, Alan L. Cox, Scott Rixner, Partha Ranganathan, Jose Renato Santos HP Laboratories H...
Kaushik Kumar Ram, Jayaram Mudigonda, Alan L. Cox,...
CASES
2008
ACM
13 years 9 months ago
A light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronization
While technology advances have made MPSoCs a standard architecture for embedded systems, their applicability is increasingly being challenged by dramatic increases in the amount o...
Chengmo Yang, Alex Orailoglu
DSD
2002
IEEE
103views Hardware» more  DSD 2002»
14 years 18 days ago
On the Fundamental Design Gap in Terabit per Second Packet Switching
We discuss the gap we experience in an industrial design path of high-speed packet switches. As bandwidth demand exceeds progress in CMOS technology, system architects are forced ...
M. Verhappen, P. H. A. van der Putten, Jeroen Voet...
JTAER
2007
160views more  JTAER 2007»
13 years 7 months ago
Enabling Knowledge Sharing within e-Government Back-Office Through Ontological Engineering
Nowadays, organizational innovation constitutes the government challenges for providing better and more efficient services to citizens, enterprises or other public offices. E–go...
Graciela Brusa, María Laura Caliusco, Omar ...
CDES
2008
90views Hardware» more  CDES 2008»
13 years 9 months ago
Nanocompilation for the Cell Matrix Architecture
- The Cell Matrix Architecture is a massive array of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, prac...
Thomas Way, Rushikesh Katikar, Ch. Purushotham