9 search results - page 1 / 2 » Physical design implementation of segmented buses to reduce ... |
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
Abstract— The amount of energy consumed for interconnecting the IP-blocks is increasing significantly due to the suboptimal scaling of long wires. To limit this energy penalty, ...
SLIP
2006
ACM
14 years 1 months ago
2006
ACM
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
GLVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
We propose an approach for reducing the energy consumption of address buses that targets both the switching and the crosstalk components of power dissipation. The method is based ...
GLOBECOM
2010
IEEE
13 years 6 months ago
2010
IEEE
Energy efficiency is one of the crucial design criteria for wireless sensor networks. Idle listening constitutes a major part of energy waste, and thus solutions such as duty cycli...
ISCA
2007
IEEE
14 years 2 months ago
2007
IEEE
Much like multi-storey buildings in densely packed metropolises, three-dimensional (3D) chip structures are envisioned as a viable solution to skyrocketing transistor densities an...