192 search results - page 10 / 39 » Pipelined FPGA Adders |
ARITH
2007
IEEE
14 years 2 months ago
2007
IEEE
Abstract— Floating-point arithmetic is notoriously nonassociative due to the limited precision representation which demands intermediate values be rounded to fit in the availabl...
ICC
2011
IEEE
12 years 7 months ago
2011
IEEE
—This paper presents an approach to implement a high-performance 8-tap digital FIR (Finite Impulse Response) filter using the Logarithmic Number System. In the past, FIR filter...
FPGA
2004
ACM
14 years 1 months ago
2004
ACM
FPGAs normally operate at whatever clock rate is appropriate for the loaded configuration. When FPGAs are used as computational devices in a larger system, however, it is better ...
ASAP
2006
IEEE
14 years 2 months ago
2006
IEEE
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this boun...
FPGA
1997
ACM
14 years 2 days ago
1997
ACM
This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250 MHz cross-correlator for radio astronomy. Experimental resu...