192 search results - page 21 / 39 » Pipelined FPGA Adders |
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation o...
TC
2010
13 years 6 months ago
2010
—A dynamic multiway segment tree (DMST) is proposed for IP lookups in this paper. DMST is designed for dynamic routing tables that can dynamically insert and delete prefixes. DMS...
IPPS
1999
IEEE
14 years 7 days ago
1999
IEEE
Abstract. This paper proposes a method for implementing fractal image compression on dynamically reconfigurable architecture. In the encoding of this compression, metric computatio...
ICCD
1997
IEEE
14 years 4 days ago
1997
IEEE
In this paper, we present a parallel-array implementation of a new non-restoring square root algorithm (PASQRT). The carry-save adder (CSA) is used in the parallel array. The PASQ...
FPGA
2009
ACM
14 years 2 months ago
2009
ACM
This paper presents a hardware architecture for face detection based system on AdaBoost algorithm using Haar features. We describe the hardware design techniques including image s...