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IPPS
2000
IEEE
13 years 11 months ago
The Memory Bandwidth Bottleneck and its Amelioration by a Compiler
As the speed gap between CPU and memory widens, memory hierarchy has become the primary factor limiting program performance. Until now, the principal focus of hardware and softwar...
Chen Ding, Ken Kennedy
IPPS
2000
IEEE
13 years 11 months ago
Switch Scheduling in the Multimedia Router (MMR)
The primary goal of the Multimedia Router (MMR) project is the design and implementation of a router optimized for multimedia applications. The router is targeted for use in clust...
Damon S. Love, Sudhakar Yalamanchili, José ...
AGENTS
2000
Springer
13 years 11 months ago
Dataflow plan execution for software agents
Recent research has made it possible to build information agents that retrieve and integrate information from the World Wide Web. Although there now exist solutions for modeling W...
Greg Barish, Dan DiPasquo, Craig A. Knoblock, Stev...
MICRO
1999
IEEE
98views Hardware» more  MICRO 1999»
13 years 11 months ago
Instruction Fetch Mechanisms for Multipath Execution Processors
Branch mispredictions can have a major performance impact on high-performance processors. Multipath execution has recently been introduced to help limit the misprediction penaltie...
Artur Klauser, Dirk Grunwald
GLVLSI
1998
IEEE
122views VLSI» more  GLVLSI 1998»
13 years 11 months ago
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
Luca Benini, Giovanni De Micheli, Alberto Macii, E...