142 search results - page 15 / 29 » Polymorphic On-Chip Networks |
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the dri...
IPPS
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper describes a new parallel algorithm for Minimum Cost Path computation on the Polymorphic Processor Array, a massively parallel architecture based on a reconfigurable mesh...
ERSA
2006
13 years 9 months ago
2006
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
Conventional oblivious routing algorithms are either not application-aware or assume that each flow has its own private channel to ensure deadlock avoidance. We present a framewo...
SLIP
2006
ACM
14 years 1 months ago
2006
ACM
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...