10 search results - page 2 / 2 » Post-Layout Logic Restructuring for Performance Optimization |
GLVLSI
2008
IEEE
14 years 4 months ago
2008
IEEE
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
DAC
2010
ACM
13 years 5 months ago
2010
ACM
This paper presents a logic restructuring technique named node addition and removal (NAR). It works by adding a node into a circuit to replace an existing node and then removing t...
ICCD
2004
IEEE
2004
IEEE
Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation
14 years 7 months ago
In this paper we discuss the application of circuit-based logical reasoning to simplify optimization problems expressed as integer linear programs (ILP) over circuit states. We de...
POPL
2012
ACM
12 years 6 months ago
2012
ACM
Gradual typing lets programmers evolve their dynamically typed programs by gradually adding explicit type annotations, which confer benefits like improved performance and fewer r...
EDBT
2000
ACM
14 years 2 months ago
2000
ACM
In high-dimensional query processing, the optimization of the logical page-size of index structures is an important research issue. Even very simple query processing techniques suc...