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110
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ICS
1998
Tsinghua U.
15 years 6 months ago
Load Execution Latency Reduction
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
Bryan Black, Brian Mueller, Stephanie Postal, Ryan...
P2P
2008
IEEE
135views Communications» more  P2P 2008»
15 years 9 months ago
Popularity-Aware Prefetch in P2P Range Caching
Unstructured peer-to-peer infrastructure has been widely employed to support large-scale distributed applications. Many of these applications, such as locationbased services and m...
Qiang Wang, Khuzaima Daudjee, M. Tamer Özsu
112
Voted
IEEEPACT
2005
IEEE
15 years 8 months ago
Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors
This paper proposes a new hardware technique for using one core of a CMP to prefetch data for a thread running on another core. Our approach simply executes a copy of all non-cont...
Ilya Ganusov, Martin Burtscher
130
Voted
DSN
2006
IEEE
15 years 6 months ago
Empirical and Analytical Evaluation of Systems with Multiple Unreliable Servers
We construct, analyze and solve models of systems where a number of servers offer services to an incoming stream of demands. Each server goes through alternating periods of being ...
Jennie Palmer, Isi Mitrani
CIDR
2007
111views Algorithms» more  CIDR 2007»
15 years 4 months ago
The Case for a Signal-Oriented Data Stream Management System
Sensors capable of sensing phenomena at high data rates—on the order of tens to hundreds of thousands of samples per second—are useful in many industrial, civil engineering, s...
Lewis Girod, Yuan Mei, Ryan Newton, Stanislav Rost...