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ISCAS
2011
IEEE
248views Hardware» more  ISCAS 2011»
13 years 1 months ago
SNR measurement based on linearity test for ADC BIST
—Linearity and spectral performance test contributes most cost of ADC test. This paper presents a new method for testing an ADC’s SNR from its linearity test data. The method d...
Jingbo Duan, Degang Chen
ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
14 years 6 months ago
A Novel Low-Power Scan Design Technique Using Supply Gating
— Reduction in test power is important to improve battery life in portable devices employing periodic self-test, to increase reliability of testing and to reduce test-cost. In sc...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukh...
ICCD
2002
IEEE
108views Hardware» more  ICCD 2002»
14 years 6 months ago
Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding
Low power design techniques have been employed for more than two decades, however an emerging problem is satisfying the test power constraints for avoiding destructive test and im...
Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nic...
ICCAD
1992
IEEE
148views Hardware» more  ICCAD 1992»
14 years 1 months ago
McPOWER: a Monte Carlo approach to power estimation
Excessive power dissipation in integrated circuits causes overheating and can lead to soft errors and or permanent damage. The severity of the problem increases in proportion to t...
Richard Burch, Farid N. Najm, Ping Yang, Timothy N...
FSTTCS
2009
Springer
14 years 4 months ago
The Power of Depth 2 Circuits over Algebras
We study the problem of polynomial identity testing (PIT) for depth 2 arithmetic circuits over matrix algebra. We show that identity testing of depth 3 (ΣΠΣ) arithmetic circuit...
Chandan Saha, Ramprasad Saptharishi, Nitin Saxena