Sciweavers

462 search results - page 20 / 93
» Power Efficient Data Cache Designs
Sort
View
CODES
2008
IEEE
14 years 2 months ago
Holistic design and caching in mobile computing
We utilize application trends analysis, focused on webpage content, in order to examine the design of mobile computers more holistically. We find that both Internet bandwidth and ...
Mwaffaq Otoom, JoAnn M. Paul
DATE
2002
IEEE
100views Hardware» more  DATE 2002»
14 years 1 months ago
AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors
This paper describes the AccuPower toolset -- a set of simulation tools accurately estimating the power dissipation within a superscalar microprocessor. AccuPower uses a true hard...
Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
TCOS
2010
13 years 3 months ago
Green Secure Processors: Towards Power-Efficient Secure Processor Design
With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the softwar...
Siddhartha Chhabra, Yan Solihin
JEC
2006
71views more  JEC 2006»
13 years 8 months ago
Destructive-read in embedded DRAM, impact on power consumption
This paper explores power consumption for destructive-read embedded DRAM. Destructive-read DRAM is based on conventional DRAM design, but with sense amplifiers optimized for lower ...
Haakon Dybdahl, Per Gunnar Kjeldsberg, Marius Gran...
EUROPAR
2008
Springer
13 years 10 months ago
Performance Implications of Cache Affinity on Multicore Processors
Cache affinity between a process and a processor is observed when the processor cache has accumulated some amount of the process state, i.e., data or instructions. Cache affinity i...
Vahid Kazempour, Alexandra Fedorova, Pouya Alagheb...