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ISCA
2006
IEEE
162views Hardware» more  ISCA 2006»
14 years 2 months ago
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communicati...
Feihui Li, Chrysostomos Nicopoulos, Thomas D. Rich...
CF
2005
ACM
13 years 10 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen
MONET
2002
95views more  MONET 2002»
13 years 8 months ago
On Improving the Performance of Cache Invalidation in Mobile Environments
Many cache management schemes designed for mobile environments are based on invalidation reports (IRs). However, IR-based approach suffers from long query latency and it cannot eff...
Guohong Cao
PVLDB
2010
146views more  PVLDB 2010»
13 years 3 months ago
HaLoop: Efficient Iterative Data Processing on Large Clusters
The growing demand for large-scale data mining and data analysis applications has led both industry and academia to design new types of highly scalable data-intensive computing pl...
Yingyi Bu, Bill Howe, Magdalena Balazinska, Michae...
ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
14 years 5 months ago
Design and Implementation of Scalable Low-Power Montgomery Multiplier
In this paper, an efficient Montgomery multiplier is introduced for the modular exponentiation operation, which is fundamental to numerous public-key cryptosystems. Four aspects a...
Hee-Kwan Son, Sang-Geun Oh