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ARC
2006
Springer
124views Hardware» more  ARC 2006»
14 years 6 days ago
A Flexible Multi-port Caching Scheme for Reconfigurable Platforms
Abstract. Memory accesses contribute sunstantially to aggregate system delays. It is critical for designers to ensure that the memory subsystem is designed efficiently, and much wo...
Su-Shin Ang, George A. Constantinides, Peter Y. K....
CORR
2008
Springer
125views Education» more  CORR 2008»
13 years 8 months ago
Cross-Layer Link Adaptation Design for Relay Channels with Cooperative ARQ Protocol
The cooperative automatic repeat request (C-ARQ) is a link layer relaying protocol which exploits the spatial diversity and allows the relay node to retransmit the source data pac...
Morteza Mardani, Jalil S. Harsini, Farshad Lahouti
MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
14 years 2 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...
IPPS
2007
IEEE
14 years 2 months ago
Leakage Energy Reduction in Value Predictors through Static Decay
As process technology advances toward deep submicron (below 90nm), static power becomes a new challenge to address for energy-efficient high performance processors, especially for...
Juan M. Cebrian, Juan L. Aragón, José...
EDBT
2010
ACM
143views Database» more  EDBT 2010»
13 years 11 months ago
Efficient and scalable multi-geography route planning
This paper considers the problem of Multi-Geography Route Planning (MGRP) where the geographical information may be spread over multiple heterogeneous interconnected maps. We firs...
Vidhya Balasubramanian, Dmitri V. Kalashnikov, Sha...