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MICRO
2009
IEEE
133views Hardware» more  MICRO 2009»
14 years 4 months ago
A tagless coherence directory
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin...
DOLAP
2005
ACM
13 years 11 months ago
Parallel querying of ROLAP cubes in the presence of hierarchies
Online Analytical Processing is a powerful framework for the analysis of organizational data. OLAP is often supported by a logical structure known as a data cube, a multidimension...
Frank K. H. A. Dehne, Todd Eavis, Andrew Rau-Chapl...
ICDCS
2007
IEEE
14 years 4 months ago
STEP: Sequentiality and Thrashing Detection Based Prefetching to Improve Performance of Networked Storage Servers
State-of-the-art networked storage servers are equipped with increasingly powerful computing capability and large DRAM memory as storage caches. However, their contribution to the...
Shuang Liang, Song Jiang, Xiaodong Zhang
CSREAESA
2006
13 years 11 months ago
Power Optimization of Interconnection Networks for Transport Triggered Architecture
Transport triggered architecture (TTA) has been shown to provide an efficient way to design application specific instruction set processors. However, the interconnection network of...
Xue-mi Zhao, Zhiying Wang
APCCAS
2006
IEEE
229views Hardware» more  APCCAS 2006»
14 years 3 months ago
Low Power Combinational Multipliers using Data-driven Signal Gating
— A data driven approach to design and optimization of low power combinational multipliers is presented. This technique depends on signal gating to avoid un-necessary computation...
Nima Honarmand, Ali Afzali-Kusha