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ISCA
2010
IEEE
336views Hardware» more  ISCA 2010»
13 years 11 months ago
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...
DASC
2006
IEEE
13 years 11 months ago
Automated Caching of Behavioral Patterns for Efficient Run-Time Monitoring
Run-time monitoring is a powerful approach for dynamically detecting faults or malicious activity of software systems. However, there are often two obstacles to the implementation...
Natalia Stakhanova, Samik Basu, Robyn R. Lutz, Joh...
HPCA
2009
IEEE
14 years 7 months ago
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
Niti Madan, Li Zhao, Naveen Muralimanohar, Anirudd...
NOCS
2007
IEEE
14 years 1 months ago
The Power of Priority: NoC Based Distributed Cache Coherency
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginos...
NOSSDAV
2009
Springer
14 years 1 months ago
Power efficient real-time disk scheduling
Hard-disk drive power consumption reduction methods focus mainly on increasing the amount of time the disk is in standby mode (disk spun down) by implementing aggressive data read...
Damien Le Moal, Donald Molaro, Jorge Campello