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ISPDC
2010
IEEE
13 years 5 months ago
Resource-Aware Compiler Prefetching for Many-Cores
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
George C. Caragea, Alexandros Tzannes, Fuat Keceli...
SC
2009
ACM
14 years 2 months ago
OddCI: on-demand distributed computing infrastructure
The availability of large quantities of processors is a crucial enabler of many-task computing. Voluntary computing systems have proven that it is possible to build computing plat...
Rostand Costa, Francisco V. Brasileiro, Guido Lemo...
DAC
2010
ACM
13 years 7 months ago
Instruction cache locking using temporal reuse profile
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
Yun Liang, Tulika Mitra
EDBT
2004
ACM
143views Database» more  EDBT 2004»
14 years 7 months ago
OGSA-DQP: A Service for Distributed Querying on the Grid
OGSA-DQP is a distributed query processor exposed to users as an Open Grid Services Architecture (OGSA)-compliant Grid service. This service supports the compilation and evaluation...
M. Nedim Alpdemir, Arijit Mukherjee, Anastasios Go...
ACMMSP
2004
ACM
92views Hardware» more  ACMMSP 2004»
14 years 26 days ago
Instruction combining for coalescing memory accesses using global code motion
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
Motohiro Kawahito, Hideaki Komatsu, Toshio Nakatan...