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SBACPAD
2008
IEEE
126views Hardware» more  SBACPAD 2008»
16 years 4 days ago
A Software Transactional Memory System for an Asymmetric Processor Architecture
Due to the advent of multi-core processors and the consequent need for better concurrent programming abstractions, new synchronization paradigms have emerged. A promising one, kno...
Felipe Goldstein, Alexandro Baldassin, Paulo Cento...
ICMCS
2005
IEEE
158views Multimedia» more  ICMCS 2005»
15 years 11 months ago
Processor Load Analysis for Mobile Multimedia Streaming: The Implication of Power Reduction
The software codec on mobile device introduces significant power consumption because the energy efficiency of general processor based system is much lower than that of the dedicat...
Min Li, Xiaobo Wu, Zihua Guo, Richard Yao, Xiaolan...
EUROPAR
2005
Springer
15 years 11 months ago
Value Compression for Efficient Computation
A processor’s energy consumption can be reduced by compressing values (data and addresses) that flow through a processor pipeline and gating off portions of data path elements th...
Ramon Canal, Antonio González, James E. Smi...
IPPS
2007
IEEE
16 years 2 days ago
On the Path to Enable Multi-scale Biomolecular Simulations on PetaFLOPS Supercomputer with Multi-core Processors
1 Biological processes occurring inside cell involve multiple scales of time and length; many popular theoretical and computational multi-scale techniques utilize biomolecular simu...
Sadaf R. Alam, Pratul K. Agarwal
89
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DATE
2008
IEEE
123views Hardware» more  DATE 2008»
16 years 7 days ago
Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor
Janar Thoguluva, Anand Raghunathan, Srimat T. Chak...