1238 search results - page 99 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
131
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ASAP
2002
IEEE
15 years 11 months ago
2002
IEEE
This paper introduces PAPA: Packed Arithmetic on a Prefix Adder, a new approach to parallel prefix adder design that supports a wide variety of packed arithmetic computations, inc...
154
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EH
1999
IEEE
15 years 10 months ago
1999
IEEE
MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity, dynamic reco...
173
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CCGRID
2009
IEEE
15 years 10 months ago
2009
IEEE
This paper presents an eco-friendly daemon that reduces power and energy consumption while better maintaining high performance via an accurate workload characterization that infer...
152
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CAL
2006
15 years 6 months ago
2006
Multiple core designs have become commonplace in the processor market, and are hence a major focus in modern computer architecture research. Thus, for both product development and ...
185
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ISPAN
1997
IEEE
15 years 10 months ago
1997
IEEE
The thesis of this research is that the task of exposing the parallelism in a given application should be left to the algorithm designer, who has intimate knowledge of the applica...